ES 210 Digital Circuit and Logic Design Lab
Instructor: Ali Kujoory, Ph.D.
Spring 2018

Lab: Tue 2:30-5:00 PM, Salazar 2005
Office Hours: Tue 1:45-2:15 PM, 5:00-5:30 PM, Thu 3:00-4:00 PM; or by appointment
Office: Salazar 2010C
Phone: (707) 664-2030

Course Catalogue Description: Lab, 3 hours: Hands-on experience for logic gates, combinatorial logic, analysis and design of combinatorial circuits, electronic circuits for various logic gates, flip-flops, registers, and counters, sequential circuits and state machines. This course fulfills GE A3

Prerequisites: EE 112, Co-req: EE 230; or consent of instructor.

Course Learning Objectives (CLOs):

  1. Learn and practice the Verilog High Description Language.
  2. Design, connect, and test various combinational circuits using logical gates.
  3. Simulate and test various combinational circuits using Verilog.
  4. Design, connect, and test various sequential circuits using flip-flops.
  5. Simulate and test various sequential circuits using Verilog.

Course Outcomes (COs): Students will:

  1. Know how to design a combinational circuit to perform certain function.
  2. Know how to write a Verilog program to simulate and test a combinational circuit.
  3. Know how to design a sequential circuit to perform certain function.
  4. Know how to write a Verilog program to simulate and test a sequential circuit.

Textbook: Same as for the lectures, "Digital Design," Morris Mano and Michael Ciletti, 5th (or 4th) ed, Pearson, 2012, ISBN-13: 978-0132774208, ISBN-10: 0132774208

Lab Conducts: Side conversations, sleeping, personal inappropriate or offensive commentary or body languages, cell phone, texting, Internet browsing, drinking and eating in the lab, are absolutely not tolerated. We are here to learn. Also please follow the General Lab Rules and Precautions for Electrical Saftey.

Special Needs: If you have emergency medical information that needs to be shared with the instructor, or require special arrangements in case the building must be evacuated, please inform the instructor. Also see

Grading Policy out of the 25% of ES 210 total
Attendance & Active Participation
Labs and Reports
Quizzes & Midterm Exam
Final Exam 20%

Grading: A >= 94, A- = 90-93, B+ = 87-89, B =84-86, B- =80-83, C+ =77-79, C- =74-76, C- =70-73, D+ =67-69, D = 64-66, D- = 60-63, F =< 60

Attendance: Attendance is mandatory. There will be no excused absences except in the case of emergencies that could be substantiated.

Class Participation: Your participation in the class / lab are very important and would help me understand how much you follow the material. I recommend that you go through the slides or lab instruction before you come to the lab, jot down your questions and ask as I go through the initial discussions.

Devices and Parts for Experiments: For the required devices and components especially the ICs for the experiments, please see list of parts in the table below. You can use your multimeter, protoboard, wires and some of the ICs from EE112.

Lab Logbook: Please bring a logbook with grid paper to draw the diagrams, collect the data your measure, your calculations and derivation for your lab report and to show to the instructor. Enter the date every time you jot your data in it. It will carry some grades.

Lab Reports: Lab reports are expected from each student, although some of the labs may be done in a group fashion. Please email your report in MS_Word as attachment 12 PM the Saturday before the following session after you performed the experiment. Late submission will receive 10 deduction points for each late day, including weekends. Lab reports will not be accepted after the graded reports are returned to the students. You may not receive any grade for the labs you did not attend or reported. For each report, you simply need to fill up the tables provided in the instruction sheet. So make sure to take notes during the lab introduction and the data you gather from the experiments. Make sure to include your observations and comments.

Late submission of the report will receive 10 points for each late day including weekends.      

Quizzes and Exams: There may be drop quizzes at the beginning of the sessions. The midterm exam will be at least one hour, and the final exam 2 hours during the class period. These tests are intended that you are always ready as you are preparing to become polished electrical engineers.

Academic Integrity:Students should be familiar with the University’s Cheating and Plagiarism policy Your own commitment to learning, as evidenced by your enrollment at Sonoma State University and the University’s policy, require you to be honest in all your academic course work. Instances of academic dishonesty will not be tolerated. Cheating on exams or plagiarism (presenting the work of another as your own, or the use of another person’s ideas without giving proper credit) will result in a failing grade and sanctions by the University. For this class, all assignments are to be completed by the individual student unless otherwise specified.

Tentative Schedule
ES 210 Lab Lab Sessions Notes
Tu 1/23 Welcome & Intro to Lab 210 List of parts
Tu 1/30 Lab1 Combinations of logical gates Linux_intro
Tu 2/6 Lab2 Verilog verilog_intro
Tu 2/13 Lab3 EX_OR, EX_NOR, Verilog  
Tu 2/20 Lab4 Encoder and Decoder, Verilog  
Tu 2/27 Lab5 Multiplexer/Demultiplexer, Verilog  
Tu 3/6 Midterm  
Tu 3/13 Lab6 Half-Adder and Full-Adder, Verilog combinational circuit design_procedure_and_examples  
Tu 3/20 Spring Break  
Tu 3/27 Lab7 Binary Multiplier, Verilog  
Tu 4/3 Lab8 Flip-Flop, Verilog  
Tu 4/10 Lab9 Ripple Counter  
Tu 4/17 Lab10 Synchronous Binary Counter  
Tu 4/24 Lab11 Logical Lock Project using sequential logic  
Tu 5/1 Review for Final Exam + Make up Lab, including Lab12 completion Submit Digital Lock Project report by the weekend for grade
Tu 5/8 Final Exam

Student Learning Outcomes vs. Course Learning Objectives:
(Support Level (0-5) 0=No support, 1=lowest support, 5=highest support)
ABET Student Outcomes Course Learning Objectives Level of Support
(a) an ability to apply knowledge of mathematics, science, and engineering  
(b) an ability to design and conduct experiments, as well as to analyze and interpret data
B, D
(c) an ability to design a system, component, or process to meet desired needs
B, D
(d) an ability to function on multi-disciplinary teams
(e) an ability to identify, formulate, and solve engineering problems
B, D
(f) an understanding of professional and ethical responsibility
(g) an ability to communicate effectively
(h) the broad education necessary to understand the impact of engineering solutions in a global and societal context
(i) a recognition of the need for, and an ability to engage in life-long learning
(j) a knowledge of contemporary issues
(k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice
A, C, E
(l) a knowledge of probability and statistics, including applications appropriate to Electrical Engineering program.     
(m) a knowledge of advanced mathematics through differential and integral calculus, linear algebra, complex variables, and discrete mathematics.     
(n) a knowledge of basic sciences, computer science, and engineering sciences necessary to analyze and design complex electrical and electronic devices, software, and systems containing hardware and software components, as appropriate to Electrical Engineering program 

Assessment Methods:

Assessment of the Student Learning

  1. Student lab reports
  2. Quizzes, Midterm and Final exams

Course Quality Assessment

  1. Student survey of the course
  2. Peer instructors feedback

Dropping and Adding:

Students are responsible for understanding the policies and procedures about add/drops, academic renewal, etc. How to Add a Class has step-by-step instructions.  Registration Information lists important deadlines and penalties for adding and dropping classes. 

Campus Policy on Disability Access for Students:

If you are a student with a disability, and think you may need academic accommodations, please contact Disability Services for Students (DSS), located in Salazar Hall, Room 1049, Voice: (707) 664-2677, TTY/TDD: (707) 664-2958, as early as possible in order to avoid a delay in receiving accommodation services.  Use of DSS services, including testing accommodations, requires prior authorization by DSS. See SSU’s policy on Disability Access for Students

Campus Policy on Disability Access for StudentsEmergency Evacuation:

Campus Policy on Disability Access for StudentsIf you are a student with a disability and you think you may require assistance evacuating a building in the event of a disaster, you should inform your instructor about the type of assistance you may require. You and your instructor should discuss your specific needs and the type of precautions that should be made in advance of such an event (i.e. assigning a buddy to guide you down the stairway). We encourage you to take advantage of these preventative measures as soon as possible and contact the Disability Services for Students office if other classroom accommodations are needed.