Binary Counters and Shift Registers


To study counter and shift register chips

  1. Binary Counter:

    One of the commonly used counters is the 74193, a 4-bit presettable up-down counter. This counter can be parallel loaded or preset with the initial value. It has two clocks, one for up-counting and the other for down-counting. The load input is used for presetting the counter and the clear input will reset it. When cascading stages, Carry should be connected to Up Count and Borrow to Down Count.

    1. Connect the outputs to the lamps and the inputs to the switches. Connect the chip for up counting. Connect the clock output to the up input and draw the timing diagram. Does the counter trigger on the positive or negative edge of the clock? What is the duration of the carry out pulse? Activate the clear and keep the up clock going. Explain what happens. Set the inputs to 1000, and activate the load. What happens? Does clear and load supersede the count?

    2. Repeat (a) for the down counter.

  2. Shift Register:

    1. The Q output of a D flip-flop is delayed one clock cycle from the input. Thus, if several D flip-flops are connected so that the output of one flip-flop is connected to the input of the next flip-flop, the input to the first flip-flop can be propagated to the next in successive clock cycles. Such an arrangement is called a shift-register. Construct a 4-bit shift register using D flip-flops­. Connect lamps to the Q output of each flip-flop. Also connect a switch as input to the first (leftmost) flip-­flop so that optionally zeros or ones can be shifted to the right. Demonstrate this shift register to your instructor.

    2. The 74194 is a 4-bit universal shift register, i.e., it can shift left or right. The initial value can be preset like the counter. Unlike the counter though, the 74194 has only a single clock. The Sl and S0 control lines as shown can control the operation of the chip:

      74194 Operation
      S0 S1 Operation
      0 0 No Operation
      0 1 Shift Left
      1 0 Shift Right
      1 1 Parallel Load

      For shift operation 'shift right serial input' is shifted into the MSB (QA) and for the left shift the 'shift left serial input' is shifted into the LSB (QD). During parallel load, the values of the parallel inputs A, B, C and D are latched into the register. All these operations are synchronized with the leading edge of the clock. A lo on clear will reset the register regardless of the clock and control line settings.

    3. Connect the outputs to the lamps; the parallel inputs, controls and serial inputs to the switches; and the clock to the input. Preset the register to 0110 and connect as a circulating right shift register. Draw the truth table.

    4. Repeat 2c for the circulating left shift operation.

  3. Ring Counter:

    In digital control logic it is sometimes necessary to generate a multiple phase clock from a single clock as shown:

    Multiple Phase Clock

    One way to accomplish this is by designing a 2-bit counter and decoding each stage. An alternate way is to load a single '1' in a 4-bit shift register and allow it to circularly shift right. This is called a ring counter.

    1. Set up your shift register as ring counter and verify its operation.

    2. Modify your ring counter such that it is self starting, i.e., no matter what the initial value of the shift register is, it will start a correct sequence after four clock pulses. Demonstrate this to your instructor.