Sequential Logic Analysis


To analyze the operation of sequential circuits, deriving their timing and state diagrams


    1. Analyze the following sequential circuit by deriving the state table and the state diagram.

      Sequential Network 1
      Figure 1 - Sequential Network 1

    2. Determine the timing diagram for J1, J2, K2, Q1, Q2 and Z
      (Assuming initially that Q1 = Q2 = 0).

      Timing Diagram for Network 1
      Figure 2 - Timing Diagram for Network 1

    3. Implement the circuit using either 7473 or 7476. Obtain the timing diagram for the inputs in 1-b. Compare results.
    4. Apply the input sequence derived in 1-c. Read the output and next states and compare the results. Demonstrate your circuit to the instructor.
  2. Repeat all of part 1 for the following circuit:

    Sequential Network 2
    Figure 3 - Sequential Network 2

    Timing Diagram for Network 2
    Figure 4 - Timing Diagram for Network 2

4 diagrams in one screen